The traditional approach to moving scan test data from chip-level pins to core-level scan channels is under pressure due to the dramatic rise in design size, design complexity, and test adaptation. To ...

In the modern era, where meeting high performance and low power targets for any complex SoC (System on Chip) is very tough, testing the SoC has become even more challenging. The purpose of several DFT ...

The complicated silicon defect types and defect distribution of new IC manufacturing technologies can result in very low yield for new designs and technology nodes. During technology qualification ...

Scan insertion to improve test coverage and reduce test pattern volume is very common in today’s DFT tools. All of the major ATPG tool vendors (Synopsys, Cadence, and Mentor) offer this approach in ...

To ensure customers receive high-quality products, engineers must consider testing strategies before they even think about a schematic diagram. These days, most engineers realize boundary scan ...

Scan diagnostics play an important role in improving yield. As technologies move below 130 nm, the IC industry has seen a significant change in the type of defects encountered. Feature-related defects ...