Imperas’ riscvOVPsim RISC-V reference model and simulator has been updated and extended for RISC-V vector instructions and now supports coverage driven verification analysis. The base version of ...
A search is underway across the industry to find the best way to speed up machine learning applications, and optimizing hardware for vector instructions is gaining traction as a key element in that ...
Imperas has extended its Risc-V reference model and simulator to cover forthcoming vector instructions and to support coverage-driven verification analysis. Called riscvOVPsim, the enhanced version ...
ARM has unveiled a new, highly flexible type of vector processing instruction that it plans to debut in HPC markets and businesses. Share on Facebook (opens in a new window) Share on X (opens in a new ...
A novel AI-acceleration paper presents a method to optimize sparse matrix multiplication for machine learning models, particularly focusing on structured sparsity. Structured sparsity involves a ...
RISC-V chip designer SiFive is introducing two new processors that the company says are designed for high-performance, energy-efficient applications such as wearables, smart home devices, virtual ...
Over at the Intel Developer Zone, James Reinders writes that additional vector instructions have now been documented for Intel AVX-512, which will be first implemented in the future Intel Xeon Phi ...
ARM has unveiled a new, highly flexible type of vector processing instruction that it plans to debut in HPC markets and businesses. Share on Facebook (opens in a new window) Share on X (opens in a new ...
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